Conventional non-volatile memory control systems attempt to use a number of different protocols to give flexibility in the range of devices that can be used by the systems. Supporting the number of different protocols involves dedicated control logic for each envisioned type of interface, and for each required interface command type. Relying on dedicated control logic for each interface protocol is not a very flexible approach, and requires expensive redesign of logic for new or slightly changed versions of the interface protocols. Alternatively, a central processing unit (CPU) can be used to allow some flexibility of low level control of the non-volatile memory interface. However, this places a high burden on the CPU and hence results in limited performance.
It would be desirable to implement non-volatile memory channel control using a general purpose programmable processor in combination with a low level programmable sequencer.